Schematic illustration of a graphene transistor prototype. This technology can be used in the conventional production technology of integrated circuits based on silicon, and is expected to contribute to the realization of ultra-low-power-consumption electronics by reducing operation voltage in future.ĭetails of this technology were presented at the 2012 International Electron Devices Meeting (IEDM 2012) held in San Francisco, U.S.A., from December 10 to 12, 2012.
In addition, its transistor polarity can be electrically controlled and inverted, which to date has not been possible for transistors. An electric current on/off ratio of approximately four orders of magnitude was demonstrated at 200 K (approximately -73 ☌).
Gate biases are applied to the two top gates independently, allowing carrier densities in the top-gated graphene regions to be effectively controlled. In the developed transistor, two electrodes and two top gates are placed on graphene and graphene between the top gates is irradiated with a helium ion beam to introduce crystalline defects. Naoki Yokoyama, Shu Nakaharai, and others, Collaborative Research Team Green Nanoelectronics Center (GNC), the Nanoelectronics Research Institute (NeRI) of the National Institute of Advanced Industrial Science and Technology (AIST) and Shinichi Ogawa and others, NeRI, AIST, have developed a graphene transistor with a new operating principle, in collaboration with Innovation Center for Advanced Nanodevices (ICAN), AIST, and Kazuhito Tsukagoshi, the International Center for Materials Nanoarchitectonics (MANA) of the National Institute for Materials Science (NIMS).
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